38 posts.
Each tenfold rise in doping moves silicon's Fermi level by 59.5 mV, since EF − Ei = kT ln(ND/ni): 0.347 eV for 10¹⁶ donors. Worked numbers, limits and mistakes.
A mod-N counter needs ⌈log₂N⌉ flip-flops: 4 for mod-10, 7 for mod-100. Why ripple counters pass through wrong counts on the way, and how to read them safely.
In breakdown a Zener's current can swing widely while its voltage barely moves, but only above a minimum. A worked regulator design shows where it stops.
Where your GATE 2027 responses and the answer key appear, how to mark each MCQ, MSQ and NAT answer against the key, and how to add up your raw marks. From the GATE 2027 brochure.
How GATE 2027 takes MCQ, MSQ and NAT answers, every key on the official virtual calculator, why you type the number before the function, and the slips that cost NAT marks. With the official calculator, the mock test and a practice calculator.
In standard AM the sideband share is μ² ÷ (2 + μ²), and μ can't pass 1 without distortion, so it tops out at 1/3. The derivation and a worked 10 V example.
A diode's small-signal resistance is rd = nVT ÷ ID: 258.5 Ω at 0.1 mA, 25.85 Ω at 1 mA, 2.585 Ω at 10 mA. The derivation, a worked example and when it fails.
Raising VCE narrows the base, so IC creeps up and the BJT's output resistance is ro ≈ VA ÷ IC. The physics, a worked 50 V example and the effect on gain.
The Gibbs overshoot: a square wave's partial sums peak near 1.179, about 9% of the jump, at any number of terms. Computed sums, a worked peak and the traps.
Each Hamming parity bit checks the positions whose binary index has that bit set, so the syndrome spells out the flipped position. A worked (7,4) example.
Don't-cares in a K-map are optional 1s, not compulsory ones. Four common mistakes, a worked example checked by brute force, and why minimal answers can differ.
A 2 pF base-collector capacitance can act like 195 pF at a CE amplifier's input. A worked Miller effect example, the bandwidth it costs and how exact it is.
Indent the Nyquist contour around the pole, then map the detour: it becomes an infinite arc closing clockwise. Worked K/(s(s+1)(s+2)) example, stable for K < 6.
An ideal integrator has infinite DC gain, so any DC input ramps it into a rail: 0.5 V into 10 kΩ and 100 nF hits −12 V in 24 ms. The offset trap and the Rf fix.
A lone zero in the Routh first column gets an ε; a whole zero row needs an auxiliary polynomial. Worked examples checked against the real roots, and the traps.
Series Q = ω0L/R falls as R rises; parallel Q = R/(ω0L) rises. Why, with one worked tank: L = 1 mH, C = 10 nF, Q = 31.6 at 10 Ω series or 10 kΩ in parallel.
Setup slack uses the slowest path and the clock period; hold slack uses the fastest path and no period. A worked 5 ns example with skew gives 0.9 and 0.05 ns.
Skin depth δ = 1/√(πfμσ) shrinks as 1/√f: copper's is 9.35 mm at 50 Hz, 66.1 µm at 1 MHz and 2.09 µm at 1 GHz. Where it comes from and what it does to a wire.
With only dependent sources, Voc and Isc are both zero, so Voc ÷ Isc gives 0 ÷ 0. Use a test source: the method, a worked GATE EC example and the usual traps.
VSWR = Vmax ÷ Vmin gives |Γ|; the first minimum's position gives its phase. Worked 50 Ω line: VSWR 3, |Γ| = 0.5, return loss 6.02 dB, ZL = 24.05 − j30.50 Ω.
A z-transform means nothing without its region of convergence: 1/(1 − az⁻¹) is aⁿu[n] or −aⁿu[−n−1]. Worked poles at 0.5 and 2, three ROCs, which is stable.
Fourier series for GATE EC, EE and IN: the trigonometric and exponential forms, symmetry shortcuts, Parseval's theorem, and three worked examples including a square wave through a filter.
GATE 2027 eligibility: third year or higher of any undergraduate degree, or a completed one, and no age limit. What the official IIT Madras brochure says, in plain language, with common cases worked through.
The GATE 2027 exam date: 6 to 7, 13 to 14 and 20 to 21 February 2027, with exam cities on 4 January and results on 19 March. The official IIT Madras dates, and how to plan backwards from them.
The GATE 2027 syllabus was revised, so use the 2027 PDF for your paper. Where IIT Madras publishes each one, the official section names for CS, EC, EE, ME and BT, and how to check a topic in a minute.
A GATE study plan for the last 90 days: start on 8 November 2026 to finish on 5 February 2027, with hours split by the official GATE marks pattern and dated phases for learning, revision and mocks.
The GATE application process, from the official brochure: the GOAPS portal, DigiLocker, documents and photo ID, payment, then city allotment, admit card and exam day. Registration timing and fees are on the official site.
A GATE CS preparation order built from the official 2027 syllabus: which of the ten sections to study first, which ones depend on each other, and a 17-week plan to the exam.
A GATE ECE preparation order built from the official 2027 EC syllabus: which of the eight sections to study first, how they depend on each other, and a 17-week plan to the exam.
GATE last month preparation, day by day: from 7 January to 5 February 2027, a revision pass, seven full-length papers with reviews, and a taper, plus how to turn mock mistakes into a plan.
The GATE 2027 marking scheme: 1 and 2-mark questions, negative marking of 1/3 and 2/3 on wrong MCQs only, no partial marks in MSQ. A fully worked score and when guessing pays.
GATE NAT questions carry no negative marking, so the marks you lose come from avoidable slips: radians, natural logs, units, early rounding and signs. Five worked examples of each mistake, with the right answer.
GATE preparation for working professionals: about 350 study hours at 20 a week before February 2027, how to split them by the official marks pattern, and what the GATE 2027 rules mean if you have a job.
GATE score calculation, step by step: the official GATE 2027 formula that turns marks out of 100 into a score anchored at 350 and 900, the qualifying-mark rule, and a fully worked example.
Network theory formulas for GATE EC and EE in one place: dividers, star-delta, first-order transients, RLC resonance and Q, complex power, two-port parameters and three-phase power, each with a worked number.
The PN junction diode for GATE EC: built-in potential, depletion width and junction capacitance with a fully worked silicon example, and the mistakes that cost marks.
Thevenin's theorem for GATE EC and EE: a two-source circuit and a bridge with a load to optimise, each worked two ways, plus maximum power transfer.
GATE papers held in more than one session are normalized before scoring. The official GATE 2027 formulas from IIT Madras, explained step by step with a worked example, including how normalized marks become your GATE score.