How Many Flip-Flops Does a Mod-N Counter Need?
At least ⌈log₂N⌉, because n flip-flops have 2ⁿ states and a mod-N counter needs N of them: 4 for a decade counter, 6 for mod-60 and 7 for mod-100. A ripple counter built that way also passes briefly through wrong counts whenever several bits change, because each flip-flop waits for the one before it, so its outputs should be read only once the ripple has settled.
What you'll learn
- Why the count is ⌈log₂N⌉, and how ring and Johnson counters trade flip-flops for simpler decoding
- How a ripple counter works, and why a change takes n flip-flop delays to settle
- A worked timing example: the transition from 0111 to 1000, with the wrong counts it shows on the way
- What the resetting trick for a mod-10 counter does, and why it adds its own glitch
- How fast a ripple counter can run if every count must be read
Conventions and assumptions
Counters count up in binary, written Q3 Q2 Q1 Q0 with Q0 the least significant bit. The ripple counter uses negative-edge-triggered T flip-flops with T = 1, so each one toggles when its clock input falls. Each flip-flop has a clock-to-Q delay tpd = 10 ns. Gate delays outside the flip-flops are ignored except where stated.
Why ⌈log₂N⌉ flip-flops?
A counter's state is the pattern of its flip-flop outputs, and n flip-flops can hold 2ⁿ patterns. A mod-N counter cycles through N distinct states, so it needs 2ⁿ ≥ N, and the smallest such n is ⌈log₂N⌉. Mod-10 needs 4, since 2³ = 8 is too few and 2⁴ = 16 is enough; mod-16 also needs 4; mod-60 needs 6; mod-100 and mod-101 need 7. When N isn't a power of 2, the counter uses N of the 2ⁿ states and must be made to skip the rest. Ring and Johnson counters spend more flip-flops to make decoding trivial: a ring counter uses N flip-flops (10 for mod-10), and a Johnson counter, which feeds back the inverted last output, uses N/2 (5 for mod-10).
Why does a ripple counter pass through wrong counts?
In a ripple counter the clock reaches only the first flip-flop. Every other flip-flop is clocked by the output of the one before, so it can't change until that output has changed. When the count rolls over several bits at once, the bits change one after another, and between the changes the outputs spell out counts that are neither the old value nor the new one. A synchronous counter, where every flip-flop shares the clock, changes all its bits within one flip-flop delay and avoids most of this, at the cost of more logic.
Worked example: from 0111 to 1000
- t = 0: the clock falls. Q0 is 1 and will fall.
- t = 10 ns: Q0 falls to 0. The outputs read 0110 (6), and Q0's falling edge clocks Q1.
- t = 20 ns: Q1 falls. The outputs read 0100 (4), and Q1's edge clocks Q2.
- t = 30 ns: Q2 falls. The outputs read 0000 (0), and Q2's edge clocks Q3.
- t = 40 ns: Q3 rises. The outputs read 1000 (8): correct, four delays after the clock.
- A decoder looking for 0100 sees a true output from 20 ns to 30 ns: a 10 ns glitch on a count that never really happened.
What about the mod-10 reset trick?
A common way to make a 4-bit ripple counter count 0 to 9 is to clear it when it reaches 1010: a NAND gate detects Q3 = 1 and Q1 = 1 and drives the asynchronous clear. The counter does go 1001, 1010, 0000, but 1010 exists for as long as it takes the gate and the clear to act, typically a few nanoseconds. It never lasts a full clock period, so it isn't one of the 10 counted states, yet it is a real glitch on the outputs, and the clear pulse itself can be too short to reset every flip-flop reliably. A synchronous design that loads 0000 on the clock edge after 1001 avoids both problems.
How fast can a ripple counter run?
For the outputs to be read correctly every count, the ripple must settle and the reading circuit must have time to capture it before the next clock edge: T ≥ n·tpd + tstrobe. With four flip-flops at 10 ns and a 10 ns strobe, T ≥ 50 ns, so the counter can be read at up to 20 MHz. As a pure frequency divider, where only the last output matters, it can run faster, because the first flip-flop only has to keep up with the clock.
Where this sits in the GATE syllabus
The GATE 2027 EC syllabus lists counters, propagation delay and critical path delay under Sequential Circuits in Section 5, Digital Circuits. Questions ask how many flip-flops a count needs, what frequency a stage outputs, and what sequence a counter with extra gates goes through.
Common mistakes
- Using log₂N without rounding up: mod-10 needs 4 flip-flops, not 3.3 or 3.
- Counting states 0 to N inclusive as N states. Counting 0 to 64 is 65 states, so it needs 7 flip-flops, not 6.
- Reading a ripple counter on the clock edge. Its outputs settle n·tpd later.
- Treating the reset state of a mod-N ripple counter as a counted state. It only flashes.
- Mixing up ring and Johnson counters: a ring counter has N states with N flip-flops, a Johnson counter 2N.
Check your understanding
- Q1. How many flip-flops does a mod-24 counter need? Answer: ⌈log₂24⌉ = 5, since 2⁴ = 16 is too few and 2⁵ = 32 is enough.
- Q2. In the 4-bit ripple counter here, which wrong counts appear on the way from 0011 to 0100? Answer: 0010 at 10 ns and 0000 at 20 ns, then 0100 at 30 ns.
- Q3. A 6-bit ripple counter has 8 ns per flip-flop, and its reader needs 12 ns. What is the highest clock at which every count can be read? Answer: T ≥ 6 × 8 + 12 = 60 ns, so about 16.7 MHz.
Related
Official source
Last verified
The GATE 2027 EC syllabus lists counters, propagation delay and critical path delay under Sequential Circuits in Section 5, Digital Circuits (checked against the official PDF from IIT Madras on 29 October 2026). Every flip-flop count and the transition timing were computed in docs/verification/ece/ripple_counter.py, which simulates the counter event by event.