GATE EC Digital Circuits Previous Year Questions with Solutions

Full question on page 27 of the official paper (PDF)

GATE 2026, Q.27

Digital Circuits1 markMSQ

How many flip-flops does a binary ripple counter need to count from 0 to 64?

One or more options are correct.

Option A: 6
Option B: 7
Option C: 4
Option D: 5

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Key idea: 65 states need $2^n \ge 65$ .

Official answer: B

Six flip-flops give $2^6 = 64$ states, one short of the 65 needed for 0 to 64, so $n = 7$ ( $2^7 = 128$ ). Option (B) only.

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Full question on page 32 of the official paper (PDF)

GATE 2026, Q.35

Digital Circuits1 markNAT

A negative-edge JK flip-flop with J and K tied high is clocked by a 10 Hz square wave. Find the frequency of Q.

JK flip-flop symbol with inputs J and K, a clock input C with a bubble (negative edge triggered), and outputs Q and Q-bar. — Figure from the official GATE 2026 EC paper, IIT Guwahati

Answer format: Hz (cycles per second), rounded off to two decimal places

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Key idea: J = K = 1 toggles Q on every clock edge, halving the frequency.

Official answer: 4.90 to 5.10

The clock has 10 falling edges a second and Q changes on each one, so Q completes 5 cycles a second: 5.00 Hz.

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Full question on page 39 of the official paper (PDF)

GATE 2026, Q.42

Digital Circuits2 marksMCQ

A 256 KB memory starts at address 2500H. What is its last address?

Option A: 2FFFH
Option B: 124FFH
Option C: 424FFH
Option D: 324FFH

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Key idea: Last address = first address + size - 1, with 256 KB = 40000H.

Official answer: C

256 KB is $256 \times 1024 = 2^{18}$ byte locations, 40000H in hex, so

2500\text{H} + 40000\text{H} - 1 = 424\text{FFH}

\begin{aligned} &2500\text{H} + 40000\text{H} - 1 \\ &\quad = 424\text{FFH} \end{aligned}

Option (C).

Full question on page 42 of the official paper (PDF)

GATE 2026, Q.45

Digital Circuits2 marksMCQ

Find the 10's complement of the decimal number 47.

Option A: 52
Option B: 53
Option C: 54
Option D: 55

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Key idea: The 10's complement of a two-digit number $N$ is $100 - N$ .

Official answer: B

For the two-digit number 47:

10^2 - 47 = 53

Equivalently, the 9's complement (52) plus 1. Option (B).

Full question on page 45 of the official paper (PDF)

GATE 2026, Q.48

Digital Circuits2 marksMCQ

A 4:1 MUX has select lines $S_1 = x$ and $S_0 = z$ and inputs $I_0 = 1$ , $I_1 = 0$ , $I_2 = 1$ , $I_3 = y$ . Find $f(x, y, z)$ .

A 4:1 multiplexer with I0 tied to 1, I1 to 0, I2 to 1 and I3 to y, select inputs S1 = x and S0 = z, and output f(x, y, z). — Figure from the official GATE 2026 EC paper, IIT Guwahati

Option A: $xz + y$
Option B: $x\bar{y} + z$
Option C: $xy + \bar{z}$
Option D: $\bar{x}y + \bar{z}$

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Key idea: Write the MUX output as a sum of select-line minterms times their inputs, then simplify.

Official answer: C

In the figure, $I_2$ is wired to the same line as $I_0$ (logic 1), and the 0 line crosses over it to $I_1$ . The MUX output is

f = \bar{x}\bar{z}\,I_0 + \bar{x}z\,I_1 + x\bar{z}\,I_2 + xz\,I_3 = \bar{x}\bar{z} + x\bar{z} + xyz

\begin{aligned} f &= \bar{x}\bar{z}\,I_0 \\ &\quad + \bar{x}z\,I_1 \\ &\quad + x\bar{z}\,I_2 \\ &\quad + xz\,I_3 \\ &= \bar{x}\bar{z} + x\bar{z} + xyz \end{aligned}

f = \bar{z} + xyz = \bar{z} + xy

The last step uses $\bar{z} + z\,(xy) = \bar{z} + xy$ . Option (C).

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Full question on page 46 of the official paper (PDF)

GATE 2026, Q.49

Digital Circuits2 marksMCQ

An 8-bit shift-left register feeds $b_7$ into a D flip-flop, and $Q \oplus 1$ feeds $b_0$ . Starting from all zeros, what does the register hold ( $b_7$ to $b_0$ ) after the 5th rising edge?

An 8-bit shift-left register, b7 to b0. b7 feeds the D input of a flip-flop; the flip-flop's Q and a constant 1 feed an XOR gate whose output is the serial input to b0. The register and the flip-flop share the clock pulse. — Figure from the official GATE 2026 EC paper, IIT Guwahati

Option A: 00011111
Option B: 10111111
Option C: 00111111
Option D: 11000011

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Key idea: The serial input is $\bar{Q}$ , and $Q$ stays 0 until a 1 reaches $b_7$ .

Official answer: A

The serial input to $b_0$ is $Q \oplus 1 = \bar{Q}$ . On each edge, the register shifts left taking in $\bar{Q}$ , while the flip-flop takes in the old $b_7$ .

Edge	Serial in	$b_7$ to $b_0$ after
1	1	00000001
2	1	00000011
3	1	00000111
4	1	00001111
5	1	00011111

$b_7$ stays 0 for the first eight edges, so Q stays 0 and a 1 enters every time. Option (A).

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Full question on page 53 of the official paper (PDF)

GATE 2026, Q.56

Digital Circuits2 marksMSQ

$f(w, x, y, z) = \sum m(0, 2, 5, 7, 8, 10, 13, 14, 15)$ , with $w$ as MSB. Which expressions equal $f$ ?

One or more options are correct.

Option A: $\bar{x}\bar{z} + xz + wxy$
Option B: $xz + wxy + w\bar{x}\bar{z} + wxy\bar{z}$
Option C: $\bar{x}\bar{z} + wxy + w\bar{x}\bar{z} + wxy\bar{z}$
Option D: $\bar{x}\bar{z} + xz + wy\bar{z}$

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Key idea: Group the minterms on a K-map; minterm 14 can be covered two ways.

Official answer: A and D

Plotting the nine minterms gives these groups:

0, 2, 8, 10 (the four corners): $\bar{x}\bar{z}$ .
5, 7, 13, 15 (x = 1, z = 1): $xz$ .
14 is left (w = 1, x = 1, y = 1, z = 0). It pairs with 15 as $wxy$ , or with 10 as $wy\bar{z}$ .

f = \bar{x}\bar{z} + xz + wxy = \bar{x}\bar{z} + xz + wy\bar{z}

\begin{aligned} f &= \bar{x}\bar{z} + xz + wxy \\ &= \bar{x}\bar{z} + xz + wy\bar{z} \end{aligned}

These are options (A) and (D). Option (B) has no term covering minterms 0 and 2 (it gives 0 at $w = 0, x = 0, z = 0$ ), and option (C) has no term covering 5 and 7. Options (A) and (D).

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Full question on page 22 of the official paper (PDF)

GATE 2025, Q.23

Digital Circuits1 markMCQ

A 3-input majority gate with inputs $X$ , $Y$ and $Z$ outputs $F = 1$ when two or more inputs are 1, and $F = 0$ when two or more are 0. Which expression gives $F$ ?

Option A: $XY + YZ + ZX$
Option B: $X \oplus Y \oplus Z$
Option C: $X + Y + Z$
Option D: $XYZ$

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Key idea: $F$ is 1 exactly when some pair of inputs are both 1.

Official answer: A

Two or more inputs are 1 exactly when at least one of the pairs $XY$ , $YZ$ or $ZX$ is 1, so $F = XY + YZ + ZX$ . Option (A).

The others fail on one row each: $X \oplus Y \oplus Z$ is 0 for $X = Y = 1$ , $Z = 0$ ; $X + Y + Z$ is 1 with a single 1; and $XYZ$ is 0 with two 1s.

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Full question on page 23 of the official paper (PDF)

GATE 2025, Q.24

Digital Circuits1 markMCQ

In the circuit in the figure, a full adder takes $X$ , $Y \oplus Z$ and a carry-in of $Z$ , and its 2-bit output is $F$ . With $Z = 1$ , the circuit works as which of these, with inputs $X$ and $Y$ ?

X goes straight into a full adder. Y and Z go into an XOR gate whose output is the full adder's second input. Z also connects to the full adder's carry-in. The full adder's 2-bit output is F. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Option A: an adder
Option B: a subtractor
Option C: a multiplier
Option D: a binary to Gray code converter

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Key idea: Adding the complement of $Y$ plus 1 is subtracting $Y$ in two's complement.

Official answer: B

With $Z = 1$ , the XOR gives $\overline{Y}$ and the carry-in is 1, so the full adder computes

X + \overline{Y} + 1

That is $X - Y$ in two's complement: the sum bit is the difference bit $X \oplus Y$ , and the carry-out is 1 when no borrow is needed ( $X \ge Y$ ). The circuit is a subtractor. Option (B). With $Z = 0$ it would add.

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Full question on page 30 of the official paper (PDF)

GATE 2025, Q.35

Digital Circuits1 markNAT

A 4-bit weighted-resistor DAC uses an ideal op-amp with feedback $R$ . Bits $b_3$ to $b_0$ (MSB to LSB) switch resistors $R$ , $2R$ , $4R$ and $8R$ from $V_{REF} = 2$ V into the inverting input, as in the figure; a switch closes when its bit is 1. By how much does the magnitude of $V_O$ change when the input goes from 1110 to 1101, in mV?

A weighted-resistor DAC. VREF = 2 V feeds four resistors R, 2R, 4R and 8R, each through a switch labelled b3, b2, b1 and b0, into the inverting input of an op-amp. The feedback resistor is R, the non-inverting input is grounded, and the output is VO. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Answer format: mV, rounded off to the nearest integer

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Key idea: Each closed switch adds $V_{REF}$ times the feedback-to-input resistance ratio, so the output is a weighted sum of the bits.

Official answer: 250

V_O = -V_{REF}\left(b_3 + \frac{b_2}{2} + \frac{b_1}{4} + \frac{b_0}{8}\right)

1110: $V_O = -2\,(1 + 0.5 + 0.25) = -3.5$ V
1101: $V_O = -2\,(1 + 0.5 + 0.125) = -3.25$ V

The output changes by 0.25 V, that is 250 mV.

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Full question on page 39 of the official paper (PDF)

GATE 2025, Q.44

Digital Circuits2 marksMCQ

A 10-bit ADC samples at 1 MHz with a full-scale voltage of 3.3 V. For a 500 kHz sinusoidal input, what are the maximum SNR (in dB, to two decimal places) and the output data rate (in Mbps)?

Option A: 61.96 and 10
Option B: 61.96 and 5
Option C: 33.36 and 10
Option D: 33.36 and 5

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Key idea: A full-scale sine quantized to $N$ bits has an SNR of $6.02N + 1.76$ dB, whatever the full-scale voltage.

Official answer: A

\text{SNR}_{max} = 6.02 \times 10 + 1.76 = 61.96\ \text{dB}

\begin{aligned} \text{SNR}_{max} &= 6.02 \times 10 + 1.76 \\ &= 61.96\ \text{dB} \end{aligned}

The full-scale voltage cancels out of the ratio. Each of the $10^6$ samples per second produces 10 bits, so the data rate is 10 Mbps. Option (A).

5 Mbps would come from using the 500 kHz signal frequency instead of the 1 MHz sampling rate.

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Full question on page 40 of the official paper (PDF)

GATE 2025, Q.45

Digital Circuits2 marksMCQ

In the positive-edge-triggered circuit in the figure, the first flip-flop's D comes from a multiplexer choosing $S$ (SEL = 1) or $P_0 = 0$ (SEL = 0). The second flip-flop's D comes from a multiplexer choosing the first flip-flop's $Q$ (SEL = 1) or $P_1 = 1$ (SEL = 0). $Y$ is the XOR of the two $\overline{Q}$ outputs. With SEL and S as in the timing diagram and no timing violations, what is the sequence of $Y$ from $T_0$ to $T_3$ ?

Two D flip-flops. The first takes its D from a 2-to-1 multiplexer with S on input 1, P0 on input 0 and SEL as select. The second takes its D from a multiplexer with the first flip-flop's Q on input 1, P1 on input 0 and SEL as select. Both are clocked by CLK. An XOR gate combines the two Q-bar outputs to give Y. Below, a timing diagram: T0 to T3 are marked at CLK's falling edges; SEL rises just after T0 and falls just after T2; S rises just after T1 and falls just after T3. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Option A: 1011
Option B: 0100
Option C: 0010
Option D: 1101

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Key idea: The flip-flops change only on rising clock edges, so read the inputs at each rising edge and the output at the instant after it.

Official answer: A

$Y = \overline{Q_1} \oplus \overline{Q_2} = Q_1 \oplus Q_2$ . The marks $T_0$ to $T_3$ are falling edges, so each comes just after a rising edge. At those rising edges:

Before $T_0$ : SEL = 0, so $Q_1 = P_0 = 0$ and $Q_2 = P_1 = 1$ . $Y = 1$ .
Before $T_1$ : SEL = 1, S = 0, so $Q_1 = S = 0$ and $Q_2$ takes the old $Q_1 = 0$ . $Y = 0$ .
Before $T_2$ : SEL = 1, S = 1, so $Q_1 = 1$ and $Q_2$ takes the old $Q_1 = 0$ . $Y = 1$ .
Before $T_3$ : SEL = 0, so $Q_1 = 0$ and $Q_2 = 1$ . $Y = 1$ .

The sequence is 1011. Option (A). The first edge loads both flip-flops, so their starting state doesn't matter.

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Full question on page 51 of the official paper (PDF)

GATE 2025, Q.62

Digital Circuits2 marksNAT

In the circuit in the figure, the first flip-flop's Q drives the second's D, and the second's Q and an input $X$ go through an AND gate back to the first flip-flop's D. The AND gate's propagation delay is 1 ns, and the flip-flops have a set-up time of 2 ns, a hold time of 0 ns and a clock-to-Q delay of 2 ns. What is the maximum clock frequency with no set-up violations, in MHz?

Two D flip-flops on a common clock CLK. The first flip-flop's Q goes to the second flip-flop's D. The second flip-flop's Q and an input X feed an AND gate, whose output loops back along the top to the first flip-flop's D. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Answer format: MHz, rounded off to the nearest integer

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Key idea: The clock period must cover the slowest register-to-register path: clock-to-Q, then the logic, then set-up.

Official answer: 200

First flip-flop to second: $2 + 0 + 2 = 4$ ns (no logic between them).
Second flip-flop through the AND gate to the first: $2 + 1 + 2 = 5$ ns.

The slower path sets the period, $T_{min} = 5$ ns, so

f_{max} = \frac{1}{5\ \text{ns}} = 200\ \text{MHz}

\begin{aligned} f_{max} &= \frac{1}{5\ \text{ns}} \\ &= 200\ \text{MHz} \end{aligned}

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Full question on page 17 of the official paper (PDF)

GATE 2024, Q.19

Digital Circuits1 markMCQ

What are the essential prime implicants of $F(A, B, C, D) = \sum m(0, 2, 5, 7, 8, 10, 12, 13, 14, 15)$ ?

Option A: $BD$ , $\overline{B}\,\overline{D}$
Option B: $BD$ , $AB$
Option C: $AB$ , $\overline{B}\,\overline{D}$
Option D: $BD$ , $\overline{B}\,\overline{D}$ , $AB$

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Key idea: A prime implicant is essential only if it covers some minterm that no other prime implicant covers.

Official answer: A

The prime implicants are $\overline{B}\,\overline{D}$ (0, 2, 8, 10), $BD$ (5, 7, 13, 15), $AB$ (12, 13, 14, 15) and $A\overline{D}$ (8, 10, 12, 14).

$\overline{B}\,\overline{D}$ is the only one covering 0 and 2: essential.
$BD$ is the only one covering 5 and 7: essential.
$AB$ 's minterms 12 and 14 are also covered by $A\overline{D}$ , and 13 and 15 by $BD$ , so it is not essential (nor is $A\overline{D}$ ).

The essential prime implicants are $BD$ and $\overline{B}\,\overline{D}$ . Option (A).

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Full question on page 23 of the official paper (PDF)

GATE 2024, Q.27

Digital Circuits1 markNAT

A machine has a 32-bit architecture with one-word instructions, 24 registers and 40 instructions. Each instruction has five fields: opcode, two source registers, one destination register and an unsigned immediate value. What is the immediate's maximum value?

Answer format: An integer

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Key idea: Give each field the fewest bits that can name all its values, and the immediate gets whatever is left.

Official answer: 2047

Opcode: 40 instructions need $\lceil\log_2 40\rceil = 6$ bits.
Registers: 24 need $\lceil\log_2 24\rceil = 5$ bits each, so 15 bits for three.
Immediate: $32 - 6 - 15 = 11$ bits.

The largest unsigned 11-bit value is $2^{11} - 1 = 2047$ .

Full question on page 24 of the official paper (PDF)

GATE 2024, Q.29

Digital Circuits1 markNAT

In a number system of base $r$ , the equation $x^2 - 12x + 37 = 0$ has $x = 8$ as one of its solutions. What is $r$ ?

Answer format: An integer

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Key idea: Rewrite the coefficients 12 and 37 as base- $r$ numerals, then substitute the root.

Official answer: 11

In base $r$ , the numeral 12 means $r + 2$ and 37 means $3r + 7$ . Substituting $x = 8$ :

64 - 8(r + 2) + (3r + 7) = 0 \;\Rightarrow\; 55 - 5r = 0 \;\Rightarrow\; r = 11

\begin{aligned} &64 - 8(r + 2) + (3r + 7) \\ &\quad = 0 \\ \Rightarrow\; 55 - 5r &= 0 \\ \Rightarrow\; r &= 11 \end{aligned}

The digits 7 and 8 need a base above 8, which $r = 11$ is. The other root is $13 - 8 = 5$ in decimal, since the roots add to $r + 2 = 13$ .

Full question on page 30 of the official paper (PDF)

GATE 2024, Q.40

Digital Circuits2 marksMCQ

A 4-bit priority encoder has inputs $D_3$ , $D_2$ , $D_1$ , $D_0$ in descending priority, and outputs $AB = 00, 01, 10, 11$ for $D_3$ , $D_2$ , $D_1$ , $D_0$ respectively. What is the expression for $B$ ?

Option A: $\overline{D_3}\,\overline{D_2}$
Option B: $\overline{D_3}D_2 + \overline{D_3}\,\overline{D_1}$
Option C: $D_3\overline{D_2} + \overline{D_3}D_1$
Option D: $\overline{D_3}\,\overline{D_1}$

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Key idea: $B$ is 1 for the codes 01 and 11, that is when $D_2$ wins or when $D_0$ wins.

Official answer: B

$D_2$ wins when $D_3 = 0$ and $D_2 = 1$ . $D_0$ wins when $D_3 = D_2 = D_1 = 0$ (with at least one input active, $D_0$ must then be 1). So

B = \overline{D_3}D_2 + \overline{D_3}\,\overline{D_2}\,\overline{D_1} = \overline{D_3}\,(D_2 + \overline{D_1}) = \overline{D_3}D_2 + \overline{D_3}\,\overline{D_1}

\begin{aligned} B &= \overline{D_3}D_2 \\ &\quad + \overline{D_3}\,\overline{D_2}\,\overline{D_1} \\ &= \overline{D_3}\,(D_2 + \overline{D_1}) \\ &= \overline{D_3}D_2 + \overline{D_3}\,\overline{D_1} \end{aligned}

Option (B).

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Full question on page 31 of the official paper (PDF)

GATE 2024, Q.41

Digital Circuits2 marksMCQ

In the circuit in the figure, a 2 × 1 MUX with a propagation delay of 10 ns has its output $Y$ fed back to input 0 directly and to input 1 through an inverter with zero delay. If $S = 1$ , what is $Y$ ?

A 2 by 1 multiplexer with select S. Its output Y loops back to input 0 directly, and through an inverter to input 1. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Option A: a square wave of frequency 100 MHz
Option B: a square wave of frequency 50 MHz
Option C: constant at 0
Option D: constant at 1

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Key idea: With S = 1 the MUX passes its own inverted output, so $Y$ flips once per propagation delay.

Official answer: B

With $S = 1$ , $Y(t) = \overline{Y(t - 10\ \text{ns})}$ : every 10 ns the output takes the opposite of its value 10 ns earlier. So it flips every 10 ns, a square wave of period 20 ns.

f = \frac{1}{20\ \text{ns}} = 50\ \text{MHz}

Option (B). One half-period is one delay, which is why it isn't 100 MHz.

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Full question on page 32 of the official paper (PDF)

GATE 2024, Q.42

Digital Circuits2 marksMCQ

In the synchronous circuit in the figure, $T_1 = Q_1 + \overline{Q_0}$ and $T_0 = Q_1 + Q_0$ , each formed by an OR gate. What is the sequence of states $Q_1Q_0$ ?

Two T flip-flops on a common clock. T1 comes from an OR gate whose inputs are Q1 and Q0-bar. T0 comes from an OR gate whose inputs are Q1 and Q0. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Option A: 00 → 10 → 11 → 00
Option B: 11 → 00 → 10 → 01 → 00
Option C: 01 → 10 → 11 → 00 → 01
Option D: 00 → 01 → 10 → 00

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Key idea: A T flip-flop toggles when T = 1 and holds when T = 0, so work out both T inputs from the present state.

Official answer: B

11: $T_1 = 1$ , $T_0 = 1$ , both toggle: 00.
00: $T_1 = 0 + 1 = 1$ , $T_0 = 0$ : 10.
10: $T_1 = 1$ , $T_0 = 1$ : 01.
01: $T_1 = 0 + 0 = 0$ , $T_0 = 1$ : 00.

From 11 the circuit runs 11 → 00 → 10 → 01 → 00 and then repeats 00 → 10 → 01. Option (B).

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Full question on page 35 of the official paper (PDF)

GATE 2024, Q.46

Digital Circuits2 marksMCQ

A full-scale sine is applied to a 10-bit ADC. The fundamental at the output has a normalised power of 1 W, and the total noise and distortion is 10 µW. What is the effective number of bits, to the nearest integer?

Option A: 7
Option B: 8
Option C: 9
Option D: 10

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Key idea: Measure SINAD in dB and invert the ideal-ADC formula $6.02N + 1.76$ .

Official answer: B

\text{SINAD} = 10\log_{10}\frac{1}{10^{-5}} = 50\ \text{dB}, \qquad \text{ENOB} = \frac{50 - 1.76}{6.02} \approx 8.01

\begin{aligned} \text{SINAD} &= 10\log_{10}\frac{1}{10^{-5}} \\ &= 50\ \text{dB}, \\ \text{ENOB} &= \frac{50 - 1.76}{6.02} \\ &\approx 8.01 \end{aligned}

To the nearest integer, 8. Option (B). The noise and distortion cost the converter about two of its ten bits.

Full question on page 16 of the official paper (PDF)

GATE 2023, Q.23

Digital Circuits1 markMCQ

In the circuit in the figure, P and Q are the inputs of a 2 × 1 multiplexer: $I_0$ is grounded, $I_1 = P$ and the select line is Q. What logical function does it realise?

A 2 by 1 multiplexer with input I0 connected to ground, input I1 connected to P, select line connected to Q, and output Y. — Figure from the official GATE 2023 EC paper, IIT Kanpur

Option A: $Y = PQ$
Option B: $Y = P + Q$
Option C: $Y = \overline{PQ}$
Option D: $Y = \overline{P + Q}$

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Key idea: A 2 × 1 multiplexer gives $Y = \bar{S} I_0 + S I_1$ .

Official answer: A

Y = \bar{Q} \cdot 0 + Q \cdot P = PQ

Y is 1 only when Q selects $I_1$ and P is 1: an AND gate. Option (A).

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Full question on page 17 of the official paper (PDF)

GATE 2023, Q.24

Digital Circuits1 markMCQ

The synchronous sequential circuit in the figure, three D flip-flops in a chain sharing one clock, works at a clock frequency of 1 GHz. What are its throughput, in Mbits/s, and its latency, in ns?

Three D flip-flops in series: Input to D0, Q0 to D1, Q1 to D2, and Q2 to Output, all clocked by CLK = 1 GHz. — Figure from the official GATE 2023 EC paper, IIT Kanpur

Option A: 1000, 3
Option B: 333.33, 1
Option C: 2000, 3
Option D: 333.33, 3

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Key idea: A new bit enters on every clock edge, and each bit needs one clock per flip-flop to reach the output.

Official answer: A

Like a pipeline, the chain accepts one new bit every clock period of 1 ns, so its throughput is one bit per ns, 1000 Mbit/s.

Each bit moves one flip-flop per clock, so it appears at $Q_2$ three clocks after it enters: a latency of 3 ns. Option (A).

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Full question on page 21 of the official paper (PDF)

GATE 2023, Q.31

Digital Circuits1 markNAT

The signal-to-noise ratio (SNR) of an ADC with a full-scale sinusoidal input is 61.96 dB. What is the resolution of the ADC, in bits?

Answer format: bits, rounded off to the nearest integer

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Key idea: For an ideal $N$ -bit ADC and a full-scale sine, $\text{SNR} = 6.02N + 1.76$ dB.

Official answer: 10

N = \frac{61.96 - 1.76}{6.02} = \frac{60.2}{6.02} = 10

\begin{aligned} N &= \frac{61.96 - 1.76}{6.02} \\ &= \frac{60.2}{6.02} \\ &= 10 \end{aligned}

The formula comes from a full-scale sine's power, $(2^N \Delta)^2/8$ , over the quantisation noise power, $\Delta^2/12$ : their ratio is $1.5 \times 4^N$ , which is $1.76 + 6.02N$ dB. Answer: 10 bits.

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Full question on page 23 of the official paper (PDF)

GATE 2023, Q.34

Digital Circuits1 markNAT

For the circuit in the figure, two cross-coupled NAND gates with inputs A and B and outputs Q and $\overline{Q}$ , the propagation delay of each NAND gate is 1 ns. What is the critical path delay, in ns?

Two NAND gates, cross-coupled: input A and the second gate's output feed the first gate, whose output is Q; input B and Q feed the second gate, whose output is Q bar. — Figure from the official GATE 2023 EC paper, IIT Kanpur

Answer format: ns, rounded off to the nearest integer

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Key idea: A change only settles once it has gone through one gate and been fed back through the other.

Official answer: 2

Pull A low to set the latch: after 1 ns the first gate's output Q goes high. Only then does the second gate see the new Q, and after another 1 ns $\overline{Q}$ goes low and holds Q. The outputs are settled after two gate delays, so the critical path is 2 ns.

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Full question on page 42 of the official paper (PDF)

GATE 2023, Q.62

Digital Circuits2 marksNAT

A sample and hold circuit uses a resistive switch and a capacitor with a time constant of 1 µs. How long must the sampling switch stay closed to charge the capacitor adequately to a full-scale voltage of 1 V with 12-bit accuracy, in µs?

Answer format: µs, rounded off to two decimal places

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Key idea: 12-bit accuracy means the remaining error, $e^{-t/\tau}$ of full scale, must fall to $2^{-12}$ .

Official answer: 8.30 to 8.34

e^{-t/\tau} = 2^{-12} \quad\Rightarrow\quad t = 12\,\tau \ln 2 = 12 \times 1\ \mu\text{s} \times 0.6931 = 8.32\ \mu\text{s}

\begin{aligned} e^{-t/\tau} &= 2^{-12} \\ \Rightarrow\; \\ t &= 12\,\tau \ln 2 \\ &= 12 \times 1\ \mu\text{s} \times 0.6931 \\ &= 8.32\ \mu\text{s} \end{aligned}

Answer: 8.32 µs. (Asking for half an LSB, $2^{-13}$ , would give 9.01 µs, which is outside the key's range.)

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Full question on page 43 of the official paper (PDF)

GATE 2023, Q.63

Digital Circuits2 marksNAT

In the sequential circuit in the figure, two D flip-flops share a 1 MHz clock, with $D_1 = Q_2$ and $D_2 = \overline{Q_1}$ . The initial states are $Q_1 = 1$ and $Q_2 = 0$ . What is the frequency of the signal $Q_2$ , in kHz?

Two D flip-flops clocked by CLK = 1 MHz. Q2 is fed back to D1 along the top, and the Q1 bar output is connected to D2. — Figure from the official GATE 2023 EC paper, IIT Kanpur

Answer format: kHz, rounded off to the nearest integer

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Key idea: Step the state $(Q_1, Q_2)$ clock by clock until it repeats; the cycle length divides the clock frequency.

Official answer: 250, or 500

On each edge, $Q_1 \leftarrow Q_2$ and $Q_2 \leftarrow \overline{Q_1}$ :

(1, 0) \to (0, 0) \to (0, 1) \to (1, 1) \to (1, 0)

\begin{aligned} (1, 0) &\to (0, 0) \\ &\to (0, 1) \\ &\to (1, 1) \\ &\to (1, 0) \end{aligned}

The state repeats every 4 clocks, and $Q_2$ is high for two of them and low for two, so it is a square wave at $1\ \text{MHz}/4 = 250$ kHz.

The key accepts 250 or 500. 500 kHz is what you get by reading $D_2$ as connected to $Q_1$ instead: then the state alternates $(1, 0) \to (0, 1) \to (1, 0)$ , a cycle of 2 clocks. The line in the figure is drawn from the $\overline{Q_1}$ output.

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