GATE EC Analog Circuits Previous Year Questions with Solutions

Full question on page 18 of the official paper (PDF)

GATE 2026, Q.18

Analog Circuits1 markMCQ

An op-amp drives a BJT's base and senses the voltage across its 1 kΩ emitter resistor, with $V_i = 3$ V at the op-amp input and $V_{CC} = 12$ V. With $V_{BE} = 0.7$ V and $\beta = 99$ , find the base current $I_o$ .

An op-amp with Vi at its non-inverting input drives the base of an NPN transistor (base current Io). The collector goes to VCC through 2 kΩ, the emitter to ground through 1 kΩ, and the emitter is fed back to the op-amp's inverting input. — Figure from the official GATE 2026 EC paper, IIT Guwahati

Option A: 60 µA
Option B: 6 µA
Option C: 3 µA
Option D: 30 µA

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Key idea: Feedback holds the emitter at $V_i$ , which fixes $I_E$ ; then $I_B = I_E/(\beta + 1)$ .

Official answer: D

The emitter sits at $V_i = 3$ V, across the 1 kΩ resistor. So

I_E = \frac{3\text{ V}}{1\text{ k}\Omega} = 3\text{ mA}, \qquad I_o = I_B = \frac{I_E}{\beta + 1} = \frac{3\text{ mA}}{100} = 30\ \mu\text{A}

\begin{aligned} I_E &= \frac{3\text{ V}}{1\text{ k}\Omega} \\ &= 3\text{ mA}, \\ I_o &= I_B \\ &= \frac{I_E}{\beta + 1} \\ &= \frac{3\text{ mA}}{100} \\ &= 30\ \mu\text{A} \end{aligned}

Check the BJT is active: $V_C = 12 - 2\text{ k}\Omega \times 2.97\text{ mA} \approx 6.06$ V, above the emitter. Option (D).

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Full question on page 47 of the official paper (PDF)

GATE 2026, Q.50

Analog Circuits2 marksMCQ

A voltage-divider biased common-emitter stage (100 kΩ and 25 kΩ divider, 5 kΩ collector, 500 Ω unbypassed and 1 kΩ bypassed in the emitter, 12 V supply, $\beta = 99$ , $V_A = 100$ V) is driven by $V_i(t) = A\cos(10^5 t) + B\sin(10^7 t)$ . Which is the best approximation of $V_o(t)$ ?

Common-emitter amplifier: Vi(t) through 100 nF to the base, biased from +12 V by 100 kΩ and 25 kΩ. The collector goes to +12 V through 5 kΩ, with the output Vo(t) taken through 100 nF. The emitter goes to ground through 500 Ω and then 1 kΩ, with 10 µF across the 1 kΩ. — Figure from the official GATE 2026 EC paper, IIT Guwahati

Option A: $-9.1[A\cos(10^5 t) + B\sin(10^7 t)]$
Option B: $9.1[A\cos(10^5 t) - B\sin(10^7 t)]$
Option C: $-190.4[A\cos(10^5 t) + B\sin(10^7 t)]$
Option D: $190.4[A\cos(10^5 t) - B\sin(10^7 t)]$

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Key idea: The capacitors are shorts at both frequencies, so both tones see the same gain $\approx -R_C/(r_e + 500)$ .

Official answer: A

Bias. The divider gives a Thévenin source of $12 \times 25/125 = 2.4$ V behind $100\,\|\,25 = 20$ kΩ. With $I_B = I_E/100$ and 1.5 kΩ in the emitter:

I_E = \frac{2.4 - 0.7}{20\text{ k}/100 + 1.5\text{ k}} = 1\text{ mA}, \qquad r_e = \frac{25\text{ mV}}{1\text{ mA}} = 25\ \Omega

\begin{aligned} I_E &= \frac{2.4 - 0.7}{20\text{ k}/100 + 1.5\text{ k}} \\ &= 1\text{ mA}, \\ r_e &= \frac{25\text{ mV}}{1\text{ mA}} \\ &= 25\ \Omega \end{aligned}

Capacitors. At $\omega = 10^5$ rad/s, the 10 µF bypass is 1 Ω against 1 kΩ, and the 100 nF input capacitor is 100 Ω against an input resistance of about 14.5 kΩ. At $10^7$ rad/s they are smaller still. Both act as shorts at both frequencies, and the output capacitor carries no current into an open output.

Gain. Only the 500 Ω stays in the emitter for signals:

A_v \approx -\frac{\alpha R_C}{r_e + 500} = -\frac{0.99 \times 5\text{ k}}{525} \approx -9.4

\begin{aligned} A_v &\approx -\frac{\alpha R_C}{r_e + 500} \\ &= -\frac{0.99 \times 5\text{ k}}{525} \\ &\approx -9.4 \end{aligned}

The same gain applies to both tones, with no phase shift between them, so

V_o(t) \approx -9.4A\cos(10^5 t) - 9.4B\sin(10^7 t)

\begin{aligned} V_o(t) &\approx -9.4A\cos(10^5 t) \\ &\quad - 9.4B\sin(10^7 t) \end{aligned}

The nearest is option (A). Option (C), $-190.4$ , is the gain with the 500 Ω bypassed as well, which the circuit doesn't do.

Note: The exact gain is $-9.40$ , not the option's $-9.1$ . The 500 Ω makes the transistor's output resistance far larger than $r_o = 100$ V/1 mA, so $r_o$ barely matters. The option's value comes from putting $r_o$ straight across $R_C$ : $(5\text{ k}\,\|\,100\text{ k})/525 \approx 9.07$ . Either way, (A) is the nearest option.

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Full question on page 50 of the official paper (PDF)

GATE 2026, Q.53

Analog Circuits2 marksMCQ

An inverting amplifier has 1 kΩ in, from $V_i = 2$ V, and 1 kΩ of feedback to a node N. N is driven from the op-amp output through 2 kΩ (current $I_X$ , towards the output) and loaded by 2 kΩ to ground. Find $I_X$ .

Inverting op-amp: Vi = 2 V through 1 kΩ to the inverting input, and 1 kΩ from the inverting input to a node. That node connects to the op-amp output through 2 kΩ, carrying IX, and to ground through 2 kΩ. The non-inverting input is grounded. — Figure from the official GATE 2026 EC paper, IIT Guwahati

Option A: 2.0 mA
Option B: 1.5 mA
Option C: 3.0 mA
Option D: 0 mA

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Key idea: The virtual ground fixes the feedback current, which fixes N's voltage; then apply KCL at N.

Official answer: C

The inverting input is a virtual ground. The input current $2\text{ V}/1\text{ k}\Omega = 2$ mA flows on through the 1 kΩ feedback resistor, so the node at its far end (call it N) sits at

V_N = 0 - 2\text{ mA} \times 1\text{ k}\Omega = -2\text{ V}

\begin{aligned} V_N &= 0 - 2\text{ mA} \times 1\text{ k}\Omega \\ &= -2\text{ V} \end{aligned}

KCL at N: 2 mA arrives through the feedback resistor, and 1 mA arrives from ground through the 2 kΩ load (since N is at $-2$ V). Both leave through the 2 kΩ towards the op-amp output, in the direction of $I_X$ :

I_X = 2 + \frac{0 - (-2)}{2} = 3\text{ mA}

The op-amp output sits at $-2 - 3 \times 2 = -8$ V. Option (C).

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Full question on page 56 of the official paper (PDF)

GATE 2026, Q.60

Analog Circuits2 marksNAT

An NMOS has its gate tied to its drain, which is fed from $V_{DD} = 5$ V through 1 kΩ ( $V_{TH} = 1$ V, $\mu C_{ox}\frac{W}{L} = 2$ mA/V², no channel-length modulation). Find the gate voltage $V_G$ .

An n-channel MOSFET with its gate tied to its drain. The drain connects to +VDD through 1 kΩ and is labelled VG; the source is grounded. — Figure from the official GATE 2026 EC paper, IIT Guwahati

Answer format: Volts, rounded off to two decimal places

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Key idea: A diode-connected MOSFET is always in saturation; equate the resistor and drain currents.

Official answer: 2.50 to 2.60

Call the gate voltage $V$ . Since $V_{DS} = V_{GS} > V_{GS} - V_{TH}$ , the transistor is saturated, and the resistor current equals the drain current (mA, V):

\frac{5 - V}{1} = \frac{1}{2}(2)(V - 1)^2 \;\Rightarrow\; V^2 - V - 4 = 0

\begin{aligned} \frac{5 - V}{1} &= \frac{1}{2}(2)(V - 1)^2 \\ \Rightarrow\; V^2 - V - 4 &= 0 \end{aligned}

V = \frac{1 + \sqrt{17}}{2} \approx 2.56\text{ V}

The other root is negative, below threshold, so it's rejected. The drain current is $5 - 2.56 = 2.44$ mA. $V_G \approx 2.56$ V.

Full question on page 57 of the official paper (PDF)

GATE 2026, Q.62

Analog Circuits2 marksNAT

An inverting amplifier has $R_1$ at the input and a T network as feedback: $R_2$ from the inverting input to a node, $R_4$ from that node to ground and $R_3$ from it to the output. All four are 50 kΩ. Find the magnitude of the closed-loop gain.

Inverting op-amp: vi through R1 to the inverting input. The feedback is a T network: R2 from the inverting input to a middle node, R4 from that node to ground, and R3 from it to the output vo. The non-inverting input is grounded. — Figure from the official GATE 2026 EC paper, IIT Guwahati

Answer format: A number (the magnitude), rounded off to two decimal places

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Key idea: Find the T's middle-node voltage from the virtual ground, then apply KCL there.

Official answer: 2.90 to 3.10

The inverting input is a virtual ground, so $v_i/R_1$ flows through $R_2$ to the T's middle node M:

V_M = -\frac{R_2}{R_1}v_i = -v_i

KCL at M: $v_i/R_1$ arrives through $R_2$ , and $R_4$ draws $V_M/R_4 = -v_i/R_4$ (it pushes current in). Both flow on through $R_3$ :

v_o = V_M - R_3\left(\frac{v_i}{R_1} + \frac{v_i}{R_4}\right) = -v_i - v_i - v_i = -3v_i

\begin{aligned} v_o &= V_M \\ &\quad - R_3\left(\frac{v_i}{R_1} + \frac{v_i}{R_4}\right) \\ &= -v_i - v_i - v_i \\ &= -3v_i \end{aligned}

In general the gain is $-\tfrac{R_2 + R_3 + R_2R_3/R_4}{R_1}$ , here $-3$ . The magnitude is 3.00.

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Full question on page 58 of the official paper (PDF)

GATE 2026, Q.65

Analog Circuits2 marksNAT

$v_i = 6\sin(\omega t)$ V drives a 10 kΩ series resistor. At the output, one branch is 10 kΩ and an ideal diode D1 to a +2 V battery; the other is an ideal diode D2 from a $-4$ V battery. Find the maximum output voltage.

A source vi(t) = 6 sin(ωt) through a 10 kΩ series resistor to the output vo(t). From the output, one branch is 10 kΩ in series with the ideal diode D1 to a 2 V battery; the other is the ideal diode D2, pointing towards the output, from a 4 V battery. — Figure from the official GATE 2026 EC paper, IIT Guwahati

Answer format: Volts, rounded off to two decimal places

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Key idea: On the positive peak D1 conducts and the two 10 kΩ resistors divide between the input and +2 V.

Official answer: 3.70 to 4.30

With no load, the output equals $v_i$ until a diode turns on.

D1 (anode towards the output, cathode on the +2 V battery) turns on when $v_o > 2$ V.
D2 (cathode on the output, anode on the battery's negative side, at $-4$ V) turns on when $v_o < -4$ V, so it only clips the negative half.

On the positive peak D1 conducts, and the two 10 kΩ resistors divide between $v_i$ and 2 V:

v_o = 2 + (v_i - 2)\frac{10}{10 + 10} = \frac{v_i + 2}{2} \;\Rightarrow\; v_{o,\max} = \frac{6 + 2}{2} = 4.00\text{ V}

\begin{aligned} v_o &= 2 \\ &\quad + (v_i - 2)\frac{10}{10 + 10} \\ &= \frac{v_i + 2}{2} \\ \Rightarrow\; v_{o,\max} &= \frac{6 + 2}{2} \\ &= 4.00\text{ V} \end{aligned}

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Full question on page 20 of the official paper (PDF)

GATE 2025, Q.21

Analog Circuits1 markMCQ

In the small-signal circuit in the figure, $v_s$ drives $r_\pi$ through $R_S$ , carrying $i_b$ , and a dependent source $\beta i_b$ flows down from the output node, which has $R_L$ to ground. What is the voltage gain $v_o / v_s$ ?

A small-signal circuit. The source vs connects through RS to r-pi, which goes to ground, with the current ib marked flowing into r-pi. A dependent current source beta ib, arrow pointing down, connects the output node vo to ground, and RL also connects vo to ground. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Option A: $-\dfrac{\beta R_L}{R_S + r_\pi}$
Option B: $+\dfrac{\beta R_L}{R_S}$
Option C: $-\dfrac{\beta R_L}{R_S}$
Option D: $+\dfrac{\beta R_L}{R_S + r_\pi}$

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Key idea: Find $i_b$ from the input loop alone, then let the dependent source drive the load.

Official answer: A

The input side is $R_S$ and $r_\pi$ in series, so

i_b = \frac{v_s}{R_S + r_\pi}

The source $\beta i_b$ pulls current down out of the output node, so that current flows up through $R_L$ and makes $v_o$ negative:

v_o = -\beta i_b R_L \;\Rightarrow\; \frac{v_o}{v_s} = -\frac{\beta R_L}{R_S + r_\pi}

\begin{aligned} v_o &= -\beta i_b R_L \\ \Rightarrow\; \frac{v_o}{v_s} &= -\frac{\beta R_L}{R_S + r_\pi} \end{aligned}

Option (A). Dropping $r_\pi$ gives (C), and missing the inversion gives (D).

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Full question on page 21 of the official paper (PDF)

GATE 2025, Q.22

Analog Circuits1 markMCQ

In the circuit in the figure, $V_{CC} = 10$ V feeds the collector through 5 kΩ, the emitter has 3 kΩ to ground, and $R_B$ connects the collector to the base. The ideal BJT is in the active region with $\beta = 100$ . If $I_B = 10$ µA, what is $V_{CE}$ in volts, to two decimal places?

A BJT bias circuit. VCC = 10 V connects through 5 kilohms to the collector. RB connects the collector node to the base, with IB flowing into the base. The emitter goes to ground through 3 kilohms. VCE is marked between collector and emitter. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Option A: 4.95
Option B: 3.03
Option C: 1.92
Option D: 3.73

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Key idea: With $R_B$ taken from the collector, the collector resistor carries the base current as well as the collector current.

Official answer: C

With $\beta = 100$ and $I_B = 10$ µA, $I_C = 1$ mA and $I_E = 1.01$ mA.

The 5 kΩ carries $I_C + I_B = 1.01$ mA, because $I_B$ leaves the collector node through $R_B$ . So

V_C = 10 - 5\,\text{k}\Omega \times 1.01\,\text{mA} = 4.95\ \text{V}, \qquad V_E = 3\,\text{k}\Omega \times 1.01\,\text{mA} = 3.03\ \text{V}

\begin{aligned} V_C &= 10 \\ &\quad - 5\,\text{k}\Omega \\ &\quad \times 1.01\,\text{mA} \\ &= 4.95\ \text{V}, \\ V_E &= 3\,\text{k}\Omega \\ &\quad \times 1.01\,\text{mA} \\ &= 3.03\ \text{V} \end{aligned}

V_{CE} = 4.95 - 3.03 = 1.92\ \text{V}

\begin{aligned} V_{CE} &= 4.95 - 3.03 \\ &= 1.92\ \text{V} \end{aligned}

Option (C). Options (A) and (B) are $V_C$ and $V_E$ on their own, and using only $I_C$ in the 5 kΩ gives 1.97 V.

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Full question on page 28 of the official paper (PDF)

GATE 2025, Q.29

Analog Circuits1 markMSQ

Which statements about an ideal op-amp are TRUE?

One or more options are correct.

Option A: It has an infinite input resistance
Option B: It has an infinite output resistance
Option C: It has an infinite open-loop differential gain
Option D: It has an infinite open-loop common-mode gain

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Key idea: An ideal op-amp amplifies only the difference between its inputs, draws no input current and drives any load.

Official answer: A and C

An ideal op-amp has infinite input resistance (A) and infinite differential gain (C). Its output resistance is zero, not infinite, so it can drive any load, and its common-mode gain is zero, since it ignores what the two inputs share (infinite CMRR). Options (A) and (C).

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Full question on page 28 of the official paper (PDF)

GATE 2025, Q.30

Analog Circuits1 markMSQ

For ideal MOSFET single-stage DC-coupled amplifiers with finite load resistors, which statements are TRUE?

One or more options are correct.

Option A: The common-gate amplifier has an infinite input resistance
Option B: The common-source amplifier has an infinite input resistance
Option C: The input and output voltages of the common-source amplifier are in phase
Option D: The input and output voltages of the common-drain amplifier are in phase

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Key idea: Whether the signal goes into the gate or the source decides the input resistance, and which terminal it comes out of decides the phase.

Official answer: B and D

(A) is false: a common-gate stage takes its input at the source, where the input resistance is about $1/g_m$ .
(B) is true: the common-source input is the gate, which draws no current.
(C) is false: the common-source gain is $-g_m R_D$ , so the output is inverted.
(D) is true: the common-drain stage (source follower) has a positive gain just under 1.

Options (B) and (D).

Full question on page 30 of the official paper (PDF)

GATE 2025, Q.34

Analog Circuits1 markNAT

In the ideal inverting filter in the figure, the input is $R$ in series with $10C$ , and the feedback is $2R$ in parallel with $0.1C$ . The lower $-3$ dB frequency is 1 MHz. What is the upper $-3$ dB frequency, in MHz?

An inverting op-amp filter. The input vs passes through R and a capacitor 10C in series into the inverting input. The feedback from the output to the inverting input is 2R in parallel with 0.1C. The non-inverting input is grounded and the output is vo. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Answer format: MHz, rounded off to the nearest integer

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Key idea: The input network sets the lower corner and the feedback network the upper one, each through its own time constant.

Official answer: 50

The gain is $-Z_f / Z_i$ , with

\frac{V_o}{V_s} = -\frac{2R}{1 + j\omega(0.2RC)} \cdot \frac{j\omega(10RC)}{1 + j\omega(10RC)}

The input network is a high-pass with its corner at $1/(2\pi \cdot 10RC)$ , and the feedback network a low-pass with its corner at $1/(2\pi \cdot 0.2RC)$ . Taking each corner as a $-3$ dB frequency, their ratio is

\frac{f_H}{f_L} = \frac{10RC}{0.2RC} = 50 \;\Rightarrow\; f_H = 50 \times 1\ \text{MHz} = 50\ \text{MHz}

\begin{aligned} \frac{f_H}{f_L} &= \frac{10RC}{0.2RC} \\ &= 50 \\ \Rightarrow\; f_H &= 50 \times 1\ \text{MHz} \\ &= 50\ \text{MHz} \end{aligned}

Note: The exact $-3$ dB points come out at about 54 MHz, because the two poles interact (the peak gain is 1.96, not 2). The key uses the standard corner-frequency approximation, which is the method expected in the exam.

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Full question on page 38 of the official paper (PDF)

GATE 2025, Q.43

Analog Circuits2 marksMCQ

In the differential pair in the figure, the identical ideal MOSFETs $M_1$ and $M_2$ are in saturation with $g_m = 5$ mS. Each drain has 1 kΩ to $V_{DD} = 5$ V, and the tail current is 2 mA. The inputs are $V_1 = 2.5 + 0.01\sin\omega t$ and $V_2 = 2.5 - 0.01\sin\omega t$ volts. What is $V_3$ , the drain voltage of $M_1$ , in volts?

A MOSFET differential pair. M1 and M2 have 1 kilohm drain resistors to VDD = 5 V, with outputs V3 at M1's drain and V4 at M2's drain. The gates take V1 and V2. The sources join at a 2 mA current source to ground. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Option A: $3 + 0.05\sin\omega t$
Option B: $3 - 0.1\sin\omega t$
Option C: $4 + 0.1\sin\omega t$
Option D: $4 - 0.05\sin\omega t$

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Key idea: The tail current splits equally at rest, and each transistor's current changes by $g_m$ times half the differential input.

Official answer: D

At rest each transistor carries half of 2 mA, so $V_3 = 5 - 1\,\text{k}\Omega \times 1\,\text{mA} = 4$ V.

The differential input is $V_1 - V_2 = 0.02\sin\omega t$ . Each transistor sees half of it, so $M_1$ 's current rises by

\Delta I_{D1} = g_m \cdot \frac{0.02\sin\omega t}{2} = 5\,\text{mS} \times 0.01\sin\omega t = 0.05\sin\omega t\ \text{mA}

\begin{aligned} \Delta I_{D1} &= g_m \cdot \frac{0.02\sin\omega t}{2} \\ &= 5\,\text{mS} \times 0.01\sin\omega t \\ &= 0.05\sin\omega t\ \text{mA} \end{aligned}

V_3 = 4 - 1\,\text{k}\Omega \times 0.05\sin\omega t\ \text{mA} = 4 - 0.05\sin\omega t\ \text{V}

\begin{aligned} V_3 &= 4 \\ &\quad - 1\,\text{k}\Omega \\ &\quad \times 0.05\sin\omega t\ \text{mA} \\ &= 4 - 0.05\sin\omega t\ \text{V} \end{aligned}

Option (D). The drain falls when the current rises, hence the minus sign; using the whole differential input gives the 0.1 in (B) and (C).

Full question on page 42 of the official paper (PDF)

GATE 2025, Q.47

Analog Circuits2 marksMCQ

In the circuit in the figure, identical PNP transistors $Q_1$ and $Q_2$ are active with $\beta = 120$ , and $V_{EB1} = V_{EB2} = 0.7$ V. $Q_2$ is diode-connected from the 20 V rail into a Zener diode in breakdown ( $V_Z = 5$ V, $I_Z = 25$ mA), which feeds $R_1$ to ground. That node drives $Q_1$ 's base; $Q_1$ 's emitter has $R_2$ to 20 V and its collector feeds the load. If $I_L = 12$ mA, what are $R_1$ and $R_2$ in kΩ, to one decimal place?

A 20 V rail. On the left, PNP Q2 has its emitter on the rail and its base tied to its collector; the collector feeds a Zener diode (IZ downward), whose lower end is a node connected to R1 to ground. On the right, R2 runs from the rail to the emitter of PNP Q1 (IE downward); Q1's base connects to the Zener node (IB flowing into the node), and its collector feeds RL to ground, carrying IL. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Option A: 0.6 and 0.4
Option B: 1.4 and 2.5
Option C: 14.0 and 25.0
Option D: 6.0 and 4.0

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Key idea: The diode drop and the Zener voltage fix $Q_1$ 's base voltage, and the base current adds to the Zener current in $R_1$ .

Official answer: A

$Q_2$ drops 0.7 V, so the Zener's top is at 19.3 V and its bottom node at $19.3 - 5 = 14.3$ V. That node is $Q_1$ 's base.

$I_L = I_{C1} = 12$ mA, so $I_B = 12/120 = 0.1$ mA and $I_E = 12.1$ mA. The base current flows out of $Q_1$ 's base into the node, joining the Zener current in $R_1$ :

R_1 = \frac{14.3}{25 + 0.1\ \text{mA}} \approx 0.57\ \text{k}\Omega \approx 0.6\ \text{k}\Omega

\begin{aligned} R_1 &= \frac{14.3}{25 + 0.1\ \text{mA}} \\ &\approx 0.57\ \text{k}\Omega \\ &\approx 0.6\ \text{k}\Omega \end{aligned}

R_2 = \frac{20 - (14.3 + 0.7)}{12.1\ \text{mA}} \approx 0.41\ \text{k}\Omega \approx 0.4\ \text{k}\Omega

\begin{aligned} R_2 &= \frac{20 - (14.3 + 0.7)}{12.1\ \text{mA}} \\ &\approx 0.41\ \text{k}\Omega \\ &\approx 0.4\ \text{k}\Omega \end{aligned}

Option (A).

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Full question on page 49 of the official paper (PDF)

GATE 2025, Q.57

Analog Circuits2 marksMSQ

All diodes in the bridge in the figure are ideal, with $R$ across the bridge and $V_O$ across $R$ . As $V_I$ is swept from $-M$ to $M$ volts, which of the plots (A) to (D) are correct?

Above: a source VI feeding a four-diode bridge, with the input current II marked, and a resistor R across the bridge's other diagonal carrying VO. Below, four plots. A: VO against VI is a V shape, 0 at the origin, rising to M at both VI = -M and VI = M. B: VO equals VI, a straight line from (-M, -M) to (M, M). C: II against VI is a V shape reaching M/R at both ends. D: II against VI is a straight line from -M/R at VI = -M to M/R at VI = M. — Figure from the official GATE 2025 EC paper, IIT Roorkee

One or more options are correct.

Option A: Plot (A)
Option B: Plot (B)
Option C: Plot (C)
Option D: Plot (D)

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Key idea: A bridge routes current through the load the same way for either input polarity, but the source current still reverses with the source.

Official answer: A and D

For $V_I > 0$ one pair of opposite diodes conducts, and for $V_I < 0$ the other pair does. Either way the current through $R$ flows the same way, so $V_O = |V_I|$ : plot (A), not (B).

The source sees $R$ in either case, but its current reverses with $V_I$ : $I_I = V_I / R$ , a straight line from $-M/R$ to $M/R$ . That is plot (D), not (C). Options (A) and (D).

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Full question on page 51 of the official paper (PDF)

GATE 2025, Q.61

Analog Circuits2 marksNAT

In the circuit in the figure, $V_I = 10\sin 100\pi t$ V drives $R$ , an ideal diode and a 5 V battery in series. The battery's negative terminal is joined to the diode's cathode and its positive terminal to the bottom of the input. For how long in each period of the input is the diode forward biased, in ms?

The input VI connects through a resistor R to the anode of a diode pointing down. The diode's cathode goes to the short (negative) plate of a 5 V battery, whose long (positive) plate connects to the bottom input terminal. — Figure from the official GATE 2025 EC paper, IIT Roorkee

Answer format: ms, rounded off to two decimal places

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Key idea: Read the battery's polarity first: here it pulls the cathode below the input's reference, so the diode conducts for most of the cycle.

Official answer: 13.32 to 13.34

The battery holds the cathode 5 V below the bottom terminal, so the ideal diode conducts whenever $V_I > -5$ V:

10\sin\theta > -5 \;\Rightarrow\; \sin\theta > -\tfrac{1}{2}

\begin{aligned} 10\sin\theta &> -5 \\ \Rightarrow\; \sin\theta &> -\tfrac{1}{2} \end{aligned}

That holds for every $\theta$ except $210° < \theta < 330°$ : for $240°$ of each $360°$ . The period is $2\pi / 100\pi = 20$ ms, so

t_{on} = \frac{240}{360} \times 20\ \text{ms} = 13.33\ \text{ms}

\begin{aligned} t_{on} &= \frac{240}{360} \times 20\ \text{ms} \\ &= 13.33\ \text{ms} \end{aligned}

Reading the battery the other way round, with the diode needing $V_I > 5$ V, gives 6.67 ms.

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Full question on page 15 of the official paper (PDF)

GATE 2024, Q.17

Analog Circuits1 markMCQ

In the circuit in the figure, the long-channel NMOS is in saturation with transconductance $g_m$ ; its drain is at AC ground, $C_1$ joins gate and source, and $C_L$ joins source and ground. Neglecting body effect, channel-length modulation and device capacitances, what is the input impedance $Z_{in}(j\omega)$ at the gate?

An NMOS transistor with its drain to ground. Capacitor C1 connects the gate to the source, and capacitor CL connects the source to ground. Zin(j omega) is measured into the gate. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Option A: $-\dfrac{g_m}{\omega^2 C_1 C_L} + \dfrac{1}{j\omega C_1} + \dfrac{1}{j\omega C_L}$
Option B: $\dfrac{g_m}{\omega^2 C_1 C_L} + \dfrac{1}{j\omega C_1} + \dfrac{1}{j\omega C_L}$
Option C: $\dfrac{1}{j\omega C_1} + \dfrac{1}{j\omega C_L}$
Option D: $-\dfrac{g_m}{\omega^2 C_1 C_L} + \dfrac{1}{j\omega C_1 + j\omega C_L}$

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Key idea: Drive a test current into the gate and follow it through $C_1$ into the source node, where the transistor adds $g_m v_{gs}$ .

Official answer: A

A test current $i$ into the gate flows through $C_1$ , so $v_{gs} = i / (j\omega C_1)$ . At the source, $i$ and the drain current $g_m v_{gs}$ both flow into $C_L$ :

v_s = \frac{i + g_m v_{gs}}{j\omega C_L} = \frac{i}{j\omega C_L} + \frac{g_m\, i}{(j\omega)^2 C_1 C_L}

\begin{aligned} v_s &= \frac{i + g_m v_{gs}}{j\omega C_L} \\ &= \frac{i}{j\omega C_L} \\ &\quad + \frac{g_m\, i}{(j\omega)^2 C_1 C_L} \end{aligned}

Z_{in} = \frac{v_{gs} + v_s}{i} = \frac{1}{j\omega C_1} + \frac{1}{j\omega C_L} - \frac{g_m}{\omega^2 C_1 C_L}

\begin{aligned} Z_{in} &= \frac{v_{gs} + v_s}{i} \\ &= \frac{1}{j\omega C_1} \\ &\quad + \frac{1}{j\omega C_L} \\ &\quad - \frac{g_m}{\omega^2 C_1 C_L} \end{aligned}

Option (A). The real part is negative: this is the negative resistance that sustains a Colpitts oscillator.

Full question on page 16 of the official paper (PDF)

GATE 2024, Q.18

Analog Circuits1 markMCQ

In the closed-loop amplifier in the figure, a MOSFET differential pair with a current-mirror load has its output tied back to the second input, and the magnitude of its open-loop low-frequency gain is 40. With all transistors in saturation, an ideal $I_{SS}$ , and body effect, channel-length modulation and device capacitances neglected, what is the closed-loop gain $v_{out}/v_{in}$ , to three decimal places?

A MOSFET differential pair with a PMOS current-mirror load from VDD and a tail current source ISS to ground. vin drives the left transistor's gate. The output vout is taken at the right drain and wired back to the right transistor's gate. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Option A: 0.976
Option B: 1.000
Option C: 1.025
Option D: 0.488

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Key idea: Feeding the whole output back to the inverting input makes a buffer whose gain is $A/(1 + A)$ .

Official answer: A

The output is fed back in full ( $\beta = 1$ ) to the input that subtracts, so

\frac{v_{out}}{v_{in}} = \frac{A}{1 + A\beta} = \frac{40}{41} \approx 0.976

\begin{aligned} \frac{v_{out}}{v_{in}} &= \frac{A}{1 + A\beta} \\ &= \frac{40}{41} \\ &\approx 0.976 \end{aligned}

Option (A). An ideal op-amp would give 1.000, option (B); the finite gain of 40 leaves about a 2.4% shortfall.

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Full question on page 20 of the official paper (PDF)

GATE 2024, Q.23

Analog Circuits1 markMCQ

In the circuit in the figure, an ideal $n : 1$ step-down transformer with a centre-tapped secondary feeds the load $R_L$ through two ideal diodes $D_1$ and $D_2$ with no forward drop. If $V_s(t) = 10\sin\omega t$ V and the average load voltage is $2.5/\pi$ V, what is $n$ ?

A source Vs(t) drives the primary of an n:1 transformer. The secondary is centre-tapped: its top end feeds diode D1 and its bottom end diode D2, both pointing right into a common node. The load RL connects the centre tap to that node, with VL(t) negative at the centre tap and positive at the node. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Option A: 4
Option B: 8
Option C: 12
Option D: 16

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Key idea: In a centre-tapped full-wave rectifier, each diode sees half the secondary, and the load sees both half-cycles.

Official answer: A

The secondary has a peak of $10/n$ V, so each half has $5/n$ V. Full-wave rectification of a peak $V_m$ averages $2V_m/\pi$ :

\frac{2}{\pi} \cdot \frac{5}{n} = \frac{2.5}{\pi} \;\Rightarrow\; n = 4

\begin{aligned} \frac{2}{\pi} \cdot \frac{5}{n} &= \frac{2.5}{\pi} \\ \Rightarrow\; n &= 4 \end{aligned}

Option (A). Taking the whole secondary as each diode's voltage gives 8, option (B).

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Full question on page 26 of the official paper (PDF)

GATE 2024, Q.35

Analog Circuits1 markNAT

In the circuit in the figure, a 10 µF capacitor starts at 10 V. At $t = 0$ a switch closes and it discharges through 10 kΩ and an ideal Zener diode with $V_Z = 5$ V, reverse biased by the capacitor. What total energy is dissipated in the Zener, in mJ?

A 10 microfarad capacitor, positive at the top with V(0-) = 10 V, a switch that closes at t = 0, a 10 kilohm resistor and a Zener diode with VZ = 5 V, all in one series loop. The capacitor drives current through the Zener in its reverse direction. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Answer format: mJ, rounded off to three decimal places

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Key idea: An ideal Zener holds exactly $V_Z$ while it conducts, so its energy is $V_Z$ times the charge that passes through it.

Official answer: 0.25

The Zener conducts in breakdown while the capacitor is above 5 V, so the capacitor falls from 10 V to 5 V and then the current stops. The charge that flows is

\Delta Q = C\,\Delta V = 10\ \mu\text{F} \times 5\ \text{V} = 50\ \mu\text{C}

\begin{aligned} \Delta Q &= C\,\Delta V \\ &= 10\ \mu\text{F} \times 5\ \text{V} \\ &= 50\ \mu\text{C} \end{aligned}

E_Z = V_Z\,\Delta Q = 5 \times 50\ \mu\text{J} = 0.250\ \text{mJ}

\begin{aligned} E_Z &= V_Z\,\Delta Q \\ &= 5 \times 50\ \mu\text{J} \\ &= 0.250\ \text{mJ} \end{aligned}

The capacitor gives up $\tfrac{1}{2}C(10^2 - 5^2) = 0.375$ mJ; the other 0.125 mJ heats the resistor.

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Full question on page 37 of the official paper (PDF)

GATE 2024, Q.49

Analog Circuits2 marksMCQ

In the circuit in the figure, the ideal op-amps saturate at ±10 V and the inductor current starts at 0. OPA1 is a non-inverting Schmitt trigger with 10 kΩ from $V_i$ and 100 kΩ of positive feedback; its output $V_{01}$ drives OPA2 through a 1 mH inductor, with 1 kΩ of feedback. $V_i$ is a triangle of ±2 V peak and 8 µs period. Which statement is true?

OPA1, with its inverting input grounded, takes Vi through 10 kilohms into its non-inverting input, with 100 kilohms from its output V01 back to that input; supplies plus and minus 10 V. V01 drives a 1 mH inductor into the inverting input of OPA2, which has 1 kilohm of feedback and a grounded non-inverting input; its output is V02. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Option A: $V_{01}$ is delayed by 2 µs relative to $V_i$ , and $V_{02}$ is a triangular waveform.
Option B: $V_{01}$ is not delayed relative to $V_i$ , and $V_{02}$ is a trapezoidal waveform.
Option C: $V_{01}$ is not delayed relative to $V_i$ , and $V_{02}$ is a triangular waveform.
Option D: $V_{01}$ is delayed by 1 µs relative to $V_i$ , and $V_{02}$ is a trapezoidal waveform.

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Key idea: Hysteresis delays each switch until the input reaches a threshold, and an integrator that reaches the rail clips its ramp.

Official answer: D

OPA1 switches when its + input crosses 0, which happens at $V_i = \pm 10 \times \frac{10}{100} = \pm 1$ V. The triangle changes by 4 V in 4 µs, 1 V/µs, so it reaches 1 V 1 µs after its zero crossing: $V_{01}$ is a ±10 V square wave delayed by 1 µs.

OPA2 with an inductor in and a resistor in feedback is an integrator: $V_{02} = -\frac{R}{L}\int V_{01}\,dt$ . Its ramp rate is $\frac{1000}{10^{-3}} \times 10 = 10^7$ V/s, so it reaches the 10 V rail in 1 µs, well inside each 4 µs half-period, and stays there:

$V_{02}$ is a trapezoid. Option (D).

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Full question on page 38 of the official paper (PDF)

GATE 2024, Q.50

Analog Circuits2 marksMCQ

In the circuit in the figure, an ideal op-amp is a non-inverting amplifier ( $R$ to ground, $R_1$ in feedback), and its output returns to the + input through a network of series $C$ , shunt $R$ , series $R$ and shunt $C$ . For sustained oscillation, what are $R_1$ and the frequency?

A non-inverting op-amp amplifier with R from the inverting input to ground and R1 from the output to the inverting input. The output feeds a series capacitor C, then a shunt resistor R to ground, then a series resistor R, then a shunt capacitor C to ground; that last node returns to the non-inverting input. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Option A: $29R$ and $1/(2\pi\sqrt{6}RC)$
Option B: $2R$ and $1/(2\pi RC)$
Option C: $29R$ and $1/(2\pi RC)$
Option D: $2R$ and $1/(2\pi\sqrt{6}RC)$

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Key idea: Oscillation needs the loop gain to be exactly 1 at the frequency where the network's phase shift is zero.

Official answer: B

Solving the two-node network with $\omega$ normalised to $1/RC$ , its transfer is real at $\omega = 1/RC$ , where

\frac{V_{fb}}{V_{out}} = \frac{1}{3}

So the amplifier must give exactly 3: $1 + R_1/R = 3$ , $R_1 = 2R$ , and the frequency is $1/(2\pi RC)$ . Option (B). The 29 and $\sqrt{6}$ in the other options belong to the three-section RC phase-shift oscillator.

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Full question on page 39 of the official paper (PDF)

GATE 2024, Q.51

Analog Circuits2 marksMCQ

In the circuit in the figure, $M_1$ and $M_2$ are in saturation with transconductances $g_{m1}$ and $g_{m2}$ . $M_1$ is diode-connected under $I_{ref}$ , and $R_B$ joins its gate to the gate of $M_2$ , which drives $R_D$ . The input $v_{in}$ reaches $M_2$ 's gate through $R_S$ and $C_1$ . Neglecting body effect, channel-length modulation and device capacitances, with $C_1$ a short for AC, what is the exact $|v_{out}/v_{in}|$ ?

M1 is diode-connected, drain and gate tied, with Iref from VDD into its drain and its source grounded. RB runs from M1's gate down to the gate of M2. vin drives M2's gate through RS and a capacitor C1. M2 has RD from VDD to its drain, where vout is taken, and its source grounded. — Figure from the official GATE 2024 EC paper, IISc Bengaluru

Option A: $g_{m2}R_D$
Option B: $\dfrac{g_{m2}R_D\left(R_B + \frac{1}{g_{m1}}\right)}{R_B + \frac{1}{g_{m1}} + R_S}$
Option C: $\dfrac{g_{m2}R_D\left(R_B + \frac{1}{g_{m1}} + R_S\right)}{R_B + \frac{1}{g_{m1}}}$
Option D: $\dfrac{g_{m2}R_D\left(\frac{1}{g_{m1}}\right)}{\frac{1}{g_{m1}} + R_S}$

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Key idea: A diode-connected MOSFET looks like a resistance of $1/g_m$ to AC, and the ideal current source above it is an open circuit.

Official answer: B

For AC, $I_{ref}$ is open and the diode-connected $M_1$ is $1/g_{m1}$ to ground. So $M_2$ 's gate sees $R_B + 1/g_{m1}$ to ground, which forms a divider with $R_S$ :

v_{g2} = v_{in}\,\frac{R_B + \frac{1}{g_{m1}}}{R_B + \frac{1}{g_{m1}} + R_S}, \qquad |v_{out}| = g_{m2}R_D\,|v_{g2}|

\begin{aligned} v_{g2} &= v_{in}\,\frac{R_B + \frac{1}{g_{m1}}}{R_B + \frac{1}{g_{m1}} + R_S}, \\ |v_{out}| &= g_{m2}R_D\,|v_{g2}| \end{aligned}

Option (B). Leaving out $R_B$ gives (D), and forgetting the divider altogether gives (A).

Full question on page 15 of the official paper (PDF)

GATE 2023, Q.21

Analog Circuits1 markMCQ

In the circuit in the figure, $V_1$ and $V_2$ are bias voltages. Based on its input and output impedances, the circuit behaves as a

A PMOS transistor with gate at bias V1 and source at VDD, its drain joined at the output vOUT to the drain of an NMOS transistor with gate at bias V2. The NMOS source connects through resistor R1 to the input source vIN, which goes to ground. — Figure from the official GATE 2023 EC paper, IIT Kanpur

Option A: voltage controlled voltage source.
Option B: voltage controlled current source.
Option C: current controlled voltage source.
Option D: current controlled current source.

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Key idea: Low input impedance means the input is a current; high output impedance means the output is a current.

Official answer: D

The NMOS is a common-gate stage: its gate is held at $V_2$ and the signal enters at its source. Looking into a source the impedance is about $1/g_m$ , which is low, so the stage takes a current as its input.

The output is taken at the drains, where the NMOS drain and the PMOS current source (gate at $V_1$ ) both look like high impedances, about $r_o$ each, so the output behaves as a current. Low input impedance and high output impedance make a current controlled current source, a current buffer. Option (D).

Full question on page 15 of the official paper (PDF)

GATE 2023, Q.22

Analog Circuits1 markMCQ

A cascade of common-source amplifiers in a unity gain feedback configuration oscillates when

Option A: the closed loop gain is less than 1 and the phase shift is less than 180°.
Option B: the closed loop gain is greater than 1 and the phase shift is less than 180°.
Option C: the closed loop gain is less than 1 and the phase shift is greater than 180°.
Option D: the closed loop gain is greater than 1 and the phase shift is greater than 180°.

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Key idea: A question given marks to all scores full marks for every candidate, whatever they answered.

Official answer: Marks to all

The key awards marks to all for this question and doesn't say why, so we don't pick an option.

The idea behind it: a feedback amplifier oscillates when the loop gain reaches 1 in magnitude at the frequency where the loop's phase shift makes the feedback positive (the Barkhausen condition). One likely reason for the ruling is that the options state the condition in terms of the closed-loop gain and a strict inequality on the phase, so none of them states the condition exactly.

Ruling in the key: The key gives marks to all (MTA) for this question: every candidate received its 1 mark.

Full question on page 26 of the official paper (PDF)

GATE 2023, Q.39

Analog Circuits2 marksMCQ

In the circuit in the figure, $v_{IN}$ drives an inverting amplifier ( $R_1$ , $R_2$ ) and a non-inverting amplifier ( $R_1$ , $R_2$ ); their outputs feed, each through $R_3$ , the inverting input of a third op-amp with feedback $R_4$ and its non-inverting input grounded. What is $V_{OUT}/V_{IN}$ ?

Op-amp circuit. The top op-amp is an inverting amplifier: v_IN through R1 to its inverting input, R2 feedback, non-inverting input grounded. The bottom op-amp is a non-inverting amplifier: v_IN to its non-inverting input, R1 from its inverting input to ground and R2 feedback. Both outputs go through resistors R3 to the inverting input of a third op-amp with feedback R4 and non-inverting input grounded; its output is v_OUT. — Figure from the official GATE 2023 EC paper, IIT Kanpur

Option A: $-\dfrac{R_4}{R_3}$
Option B: $\dfrac{R_4}{R_3}$
Option C: $1 + \dfrac{R_4}{R_3}$
Option D: $1 - \dfrac{R_4}{R_3}$

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Key idea: The third op-amp is an inverting summer, and the first two outputs add to exactly $v_{IN}$ .

Official answer: A

v_1 = -\frac{R_2}{R_1} v_{IN}, \qquad v_2 = \left(1 + \frac{R_2}{R_1}\right) v_{IN}, \qquad v_1 + v_2 = v_{IN}

\begin{aligned} v_1 &= -\frac{R_2}{R_1} v_{IN}, \\ v_2 &= \left(1 + \frac{R_2}{R_1}\right) v_{IN}, \\ v_1 + v_2 &= v_{IN} \end{aligned}

The summer gives $v_{OUT} = -\dfrac{R_4}{R_3}(v_1 + v_2) = -\dfrac{R_4}{R_3} v_{IN}$ . Option (A).

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Full question on page 27 of the official paper (PDF)

GATE 2023, Q.40

Analog Circuits2 marksMCQ

In the circuit in the figure, $D_1$ and $D_2$ are silicon diodes with a cut-in voltage of 0.7 V, connected in anti-parallel between $V_{IN}$ and $V_{OUT}$ ; $V_{OUT}$ connects through 1 kΩ to a 1 V source. Which transfer characteristic is correct?

Top: the circuit, V_IN connected to V_OUT through two diodes D1 and D2 in anti-parallel, and V_OUT connected through 1 kilohm to a 1 V source to ground. Below: four transfer characteristics A to D, as described in the options. — Figure from the official GATE 2023 EC paper, IIT Kanpur

Option A: $V_{OUT} = 1$ for $0.3 \le V_{IN} \le 1.7$ , and slope 1 outside that range
Option B: $V_{OUT} = 0$ for $-0.7 \le V_{IN} \le 0.7$ , and slope 1 outside that range
Option C: $V_{OUT} = 1$ for $-1.7 \le V_{IN} \le 1.7$ , and slope 1 outside that range
Option D: $V_{OUT} = 0$ for $0.3 \le V_{IN} \le 1.7$ , and slope 1 outside that range

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Key idea: With no diode on, no current flows in the 1 kΩ, so $V_{OUT}$ sits at 1 V.

Official answer: A

While $|V_{IN} - 1| < 0.7$ , neither diode conducts, no current flows and $V_{OUT} = 1$ V: that is $0.3 \le V_{IN} \le 1.7$ .

For $V_{IN} > 1.7$ , $D_1$ conducts and $V_{OUT} = V_{IN} - 0.7$ . For $V_{IN} < 0.3$ , $D_2$ conducts and $V_{OUT} = V_{IN} + 0.7$ . Both have slope 1, joining the flat part at 1 V. Option (A).

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Full question on page 43 of the official paper (PDF)

GATE 2023, Q.64

Analog Circuits2 marksNAT

In the circuit in the figure, a 1 mA reference flows through a diode-connected PMOS (W/L = 1). It is mirrored by PMOS devices with W/L = 10 and W/L = 7. The W/L = 10 PMOS feeds a diode-connected NMOS (W/L = 10), which is mirrored by an NMOS with W/L = 5. The output node, where the W/L = 7 PMOS and W/L = 5 NMOS drains meet, drives a 1 kΩ load to ground. What is the voltage $V_L$ , in V?

Current-mirror circuit: a 1 mA source pulls current from a diode-connected PMOS of W/L = 1 at VDD, whose gate drives two PMOS mirrors of W/L = 10 and W/L = 7. The W/L = 10 PMOS feeds a diode-connected NMOS of W/L = 10, whose gate drives an NMOS of W/L = 5. The W/L = 7 PMOS and W/L = 5 NMOS drains meet at the output V_L, which has a 1 kilohm resistor to ground. — Figure from the official GATE 2023 EC paper, IIT Kanpur

Answer format: V, rounded off to two decimal places

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Key idea: In saturation, a mirror copies the reference current scaled by the ratio of W/L.

Official answer: 2

PMOS W/L = 10: $10 \times 1 = 10$ mA, into the diode-connected NMOS of W/L = 10.
NMOS W/L = 5: $\tfrac{5}{10} \times 10 = 5$ mA, drawn from the output node.
PMOS W/L = 7: $7 \times 1 = 7$ mA, pushed into the output node.

The difference, $7 - 5 = 2$ mA, flows through the 1 kΩ, so $V_L = 2 \times 1 = 2.00$ V, assuming every transistor stays in saturation and channel-length modulation is ignored.