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Every Studyloaf post, newest first: exam guides and worked GATE ECE explainers. 62 posts in all.

Posts 13 to 24

How Does the Nyquist Criterion Handle a Pole on the jω Axis?

Indent the Nyquist contour around the pole, then map the detour: it becomes an infinite arc closing clockwise. Worked K/(s(s+1)(s+2)) example, stable for K < 6.

ECE topics•October 10, 2026•8 min read

Why Does an Op-Amp Integrator Saturate, and How Long Does It Take?

An ideal integrator has infinite DC gain, so any DC input ramps it into a rail: 0.5 V into 10 kΩ and 100 nF hits −12 V in 24 ms. The offset trap and the Rf fix.

ECE topics•October 10, 2026•7 min read

ece gate engineering-fundamentals

What Do You Do When a Routh Array Has a Zero in the First Column?

A lone zero in the Routh first column gets an ε; a whole zero row needs an auxiliary polynomial. Worked examples checked against the real roots, and the traps.

ECE topics•October 10, 2026•7 min read

ece gate engineering-fundamentals

Why Does Resistance Lower Q in Series RLC but Raise It in Parallel?

Series Q = ω0L/R falls as R rises; parallel Q = R/(ω0L) rises. Why, with one worked tank: L = 1 mH, C = 10 nF, Q = 31.6 at 10 Ω series or 10 kΩ in parallel.

ECE topics•October 10, 2026•7 min read

ece gate engineering-fundamentals

How Do You Calculate Setup and Hold Slack for a Flip-Flop Path?

Setup slack uses the slowest path and the clock period; hold slack uses the fastest path and no period. A worked 5 ns example with skew gives 0.9 and 0.05 ns.

ECE topics•October 10, 2026•7 min read

ece gate engineering-fundamentals

Why Does Copper at 1 GHz Carry Current in Only a 2 µm Layer?

Skin depth δ = 1/√(πfμσ) shrinks as 1/√f: copper's is 9.35 mm at 50 Hz, 66.1 µm at 1 MHz and 2.09 µm at 1 GHz. Where it comes from and what it does to a wire.

ECE topics•October 10, 2026•7 min read

ece gate engineering-fundamentals

How Do You Find Thevenin Resistance With No Independent Source?

With only dependent sources, Voc and Isc are both zero, so Voc ÷ Isc gives 0 ÷ 0. Use a test source: the method, a worked GATE EC example and the usual traps.

ECE topics•October 10, 2026•7 min read

ece gate engineering-fundamentals

How Do You Find a Load's Reflection Coefficient From Vmax and Vmin?

VSWR = Vmax ÷ Vmin gives |Γ|; the first minimum's position gives its phase. Worked 50 Ω line: VSWR 3, |Γ| = 0.5, return loss 6.02 dB, ZL = 24.05 − j30.50 Ω.

ECE topics•October 10, 2026•8 min read

ece gate engineering-fundamentals

Why Can the Same Z-Transform Belong to Two Different Signals?

A z-transform means nothing without its region of convergence: 1/(1 − az⁻¹) is aⁿu[n] or −aⁿu[−n−1]. Worked poles at 0.5 and 2, three ROCs, which is stable.

ECE topics•October 10, 2026•7 min read

ece gate engineering-fundamentals

Fourier Series for GATE Signals and Systems

Fourier series for GATE EC, EE and IN: the trigonometric and exponential forms, symmetry shortcuts, Parseval's theorem, and three worked examples including a square wave through a filter.

ECE topics•October 7, 2026•8 min read

gate engineering-fundamentals

GATE 2027 Eligibility, Explained with Official Links

GATE 2027 eligibility: third year or higher of any undergraduate degree, or a completed one, and no age limit. What the official IIT Madras brochure says, in plain language, with common cases worked through.

GATE•October 7, 2026•5 min read

gate eligibility

GATE 2027 Exam Date and Schedule: Every Official Date So Far

The GATE 2027 exam date: 6 to 7, 13 to 14 and 20 to 21 February 2027, with exam cities on 4 January and results on 19 March. The official IIT Madras dates, and how to plan backwards from them.

GATE•October 7, 2026•5 min read

gate exam-logistics